Integrated circuit chips frequently utilize multiple levels of patterned metallization and large numbers of electrically conductive vias to provide wiring interconnects between electronic devices embedded within an integrated circuit substrate (e.g., semiconductor substrate). In a typical case, an electrically conductive via may extend vertically through one or more electrically insulating layers to thereby provide an electrical “short” between lower and upper levels of metallization. As illustrated by FIGS. 1A-1C, one conventional technique for forming electrically conductive vias includes forming an electrically insulating layer 12 (e.g., SiO2) on a surface of a semiconductor substrate 10 having a plurality of active regions (not shown) therein that extend adjacent the surface. Conventional techniques may then be used to define a plurality of contact holes 16 that extend through the electrically insulating layer 12 and expose respective ones of the active regions (e.g., N or P-type diffusion regions). A metal layer 14 (e.g., a tungsten (W) layer) may then be conformally deposited on an upper surface of the electrically insulating layer 12 and into the contact holes 16. As illustrated, this metal layer 14, which may be of sufficient thickness to completely fill the contact holes 16, may nonetheless include a plurality of metallurgical seams 18 that identify where two facing surfaces of the metal layer 14 contact each other within the contact holes 16. These seams 18 may be present even in the absence of metal voids within the contact holes 18.
As illustrated by FIG. 1B, a portion of the metal layer 14 residing on the upper surface of the electrically insulating layer 12 may be removed to thereby define a plurality of conductive vias 20. This removal step may include chemically-mechanically polishing the metal layer 14 with a polishing slurry. The polishing step may be performed for a sufficient duration to expose the upper surface of the electrically insulating layer 12. In some instances, the polishing step may result in the formation of open seams 18′ that constitute parasitic voids within the conductive vias 20. The formation of the open seams 18′ can be an adverse consequence of using a polishing slurry containing chemical etchants that aggressively etch the metal layer 14 during the polishing step. The use of aggressive chemical etchants within the polishing slurry may also result in an excessive etch-back (i.e., recession) of the upper surfaces of the conductive vias 20, as illustrated by FIG. 1C. This excessive etch-back may occur even when the polishing step is followed immediately with a thorough cleaning step upon detecting exposure of the upper surface of the electrically insulating layer 12 during polishing. The occurrence of excessive etch-back of the conductive vias 20 may result in a lack of planarization between the upper surface of the electrically insulating layer 12 and the upper surfaces of the conductive vias 20 and thereby complicate further back-end processing steps.
One technique for chemically-mechanically polishing metal layers at purportedly high chemical etch rates is disclosed in U.S. Pat. No. 6,068,787 to Grumbine et al. The '787 patent alleges that a catalytic amount of ferric nitrate, a known oxidant, can be added to another known oxidant (e.g., hydrogen peroxide) to achieve a synergistic effect within a CMP slurry, which results in a high chemical etch rate and a high overall polishing rate for tungsten metal layers. The use of iron as a catalyst to accelerate CMP polishing is also disclosed in U.S. Pat. No. 5,948,697 to Hata. U.S. Pat. No. 5,709,593 to Guthrie et al. also discloses polishing of metallic, semiconductor and insulating layers using slurries containing reactive agents, abrasives and catalysts. Unfortunately, CMP slurries that cause high chemical etch rates may be susceptible to the excessive etch-back characteristics described above with respect to FIGS. 1A-1C.
An article by S. Basak et al., entitled “Electrochemical Aspects of the Chemical Mechanical Planarization of Tungsten,” Proceedings of the First International Symposium on Chemical Mechanical Planarization, Electrochemical Society, Vol. 96-22, pp. 137-148, also discloses using ferric nitrate in combination with hydrogen peroxide in CMP slurries. The use of ferric nitrate and other additives (e.g., complexing agents) in CMP slurries is also disclosed at section 7.3.3 and Table 7.1 of a textbook by M. R. Oliver (Ed.), entitled “Chemical-Mechanical Planarization of Semiconductor Materials,” ISBN 3-540-43181-0, Springer-Verlag (2004). One drawback to the use of ferric nitrate in CMP slurries is the generation of free Fe-ions during oxidation, which may remain as contaminants on a planarized surface after polishing and normal cleaning. As described in U.S. Pat. No. 5,662,769 to Schonauer et al., these free metal ions may be removed from a semiconductor surface using a ligand such as EDTA, which forms a highly stable complex with metal ions and thereby inhibits deposition of such free metal ions on a planarized surface.
Slurries having relatively high concentrations of abrasives may also be used to increase an overall CMP polishing rate. However, such high concentrations of abrasives may lead to high levels of micro-scratches and other defects on a planarized surface. To address this problem, additional CMP techniques, such as those disclosed in U.S. Pat. Publication No. 2002/0061635 to Lee et al., have been developed that eliminate the need for abrasives altogether.